The present invention relates to techniques for reporting output signals from a hard intellectual property block, and more particularly, to techniques for reporting output signals from a hard intellectual property block at a lower frequency.
Programmable logic devices (PLDs) are a type of programmable logic integrated circuit. Programmable logic devices can be configured to perform a variety of logical user functions. Programmable logic integrated circuits also include field programmable gate arrays (FPGAs), programmable logic arrays, configurable logic arrays, etc.
PLDs typically have numerous logic blocks that can be configured to implement various combinatorial and sequential functions. The logic blocks have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic blocks in almost any desired configuration.
Many of today's PLDs have on-chip non-programmable application specific integrated circuit (ASIC) blocks. The ASIC blocks are also referred to as hard intellectual property (HIP) blocks. A HIP block typically operates at a higher clock frequency than the programmable logic in a PLD, because the interconnect wires between programmable logic blocks usually have longer routing delays than interconnect wires in an HIP block.
Many types of HIP blocks that are used in PLDs generate error signals that indicate whether erroneous values are being generated within the HIP block. Many types of HIP blocks also generate status signals that indicate operational states of circuits in the HIP block. A HIP block typically generates the status and error signals at the same frequency as the clock signal used in the HIP block.
For a particular embodiment, the internal clock frequency inside a HIP block configured as a System Packet Interface Level 4 Phase 2 (SPI4.2) processor running at Gbps is 500 MHz. Conversely, programmable logic within a PLD or FPGA typically has to operate at a lower clock frequency (e.g., 250 MHz), a timing requirement that is a side effect of the additional delays encountered with the interconnect wires and programmable Logic Elements (LE). As a result, it is not possible for the programmable logic to capture higher frequency (500 MHz) HIP block output signals that are transmitted in a single bit stream.
One option is to lower the frequency of the HIP block's clock signal. Reducing the frequency of the HIP block's clock signal affects the operation of logic circuitry in the HIP block and can mask timing violation bugs inside the HIP block. Therefore, this option by itself is not desirable.
Therefore, it would be desirable to provide techniques for capturing output signals from a hard intellectual property (HIP) block that operates at a higher clock frequency than programmable logic on the same integrated circuit.
Hardware debugging of an HIP block is difficult because the HIP block internal clock rate is higher than the programmable logic clock rate, as described above. It is desirable for a hardware engineer to check some or all of the HIP block input clock and reset signals. However, the standard methods of signal probing are difficult in the HIP block because of the speed limitations of the FPGA standard logic elements. Therefore, it would be desirable to provide a signal from the HIP block at a lower clock frequency that indicates whether various clock and reset signals are operating properly.